EPD controller

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This page describes the Integrated EPD controller used on Freescale processors.

[edit] Overview

The EPDC is a feature-rich, low power and high performance direct drive active matrix EPD controller. It is specifically designed to drive E Ink™ EPD panels supporting a wide variety of TFT backplanes. The goal of the EPDC is to provide an efficient SoC integration of this functionality for e-paper applications, allowing a significant BOM cost saving over an external solution, while reaching much higher levels of performance at lower power. The EPDC module is defined in the context of an optimized HW/SW partitioning and works in conjunction with the PXP IP module to form a complete display processing solution.


EPDC Block diagram

[edit] Features

  • TFT resolutions up to 4096 x 4096 pixels with 20 Hz refresh (programmable up to 8191 x 8191)
  • TFT resolutions up to 1650 x 2332 pixels at 106 Hz refresh (3.8 Mpixel)
  • Industry standard bus interfaces (AMBA AXI and APB)
  • Up to 5-bit pixel representation for up to 32 grayscale levels
  • Up to 64 concurrent updates with partial update support, except for 32(5-bit) gray level panel for which only 16 concurrent updates can be used
  • Automatic collision handling when used in conjunction with the i.MX device driver
  • Dual-scan TFT drive mode to support ultra high resolution/refresh rate displays
  • Flexible direct drive TFT interface supporting next generation source driver, gate driver and panel architectures, including LVDS, DDR and multi-level source drivers
  • Unified generic configurable timing mode (Pigeon Mode) available on most panel timing control signals
  • High performance pixel pipeline architecture to guarantee refresh performance at high pixel rates without the need for high internal clocking
  • Ability to process multiple updates asynchronously to refresh/update operations with ability to intercept each frame scan will multiple update requests
  • Performance tuning capabilities which can interface with SoC level memory arbitration mechanisms further guaranteeing frame refresh operation
  • Decoupled clocking architecture allowing for independent and asynchronous clock sources for memory bus, peripheral bus and pixel clock domains
  • Full and partial update mode support
  • Support for up to 256 waveform modes, also support optimal waveform autoselection based on gray level of the pixels being updated
  • Low power mode operation via architectural clock gating
  • Update buffer analysis functions to get information like collision rectangle, gray level
  • The latest IMX7 processor supports Regal technology to minimize the need for a full refresh.

[edit] Other controllers

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